In connection with the recent miniaturization and high-functionalization of the electronic equipment, higher integration and higher densification have been required for the semiconductor integrated circuit devices to be mounted on the electronic equipment also.
To meet such the requirement as above, three-dimensional semiconductor integrated circuit devices, each of which comprises a plurality of circuit function blocks (solid-state circuits) integrated three-dimensionally, have been developed and as a result, a lot of propositions about their structure and fabrication method have been made (See Patent Literature 1).
FIG. 10 is an explanatory view showing an example of the structure of a conventional three-dimensional semiconductor integrated circuit device. This three-dimensional semiconductor integrated circuit device 300 comprises a plate-shaped base (support substrate) 370 having a solid-state circuit 371 formed in the surface region (the upper surface region in FIG. 10) thereof, and a semiconductor chip 373 having solid-state circuits 372 formed in the surface region thereof, where the chip 373 is stacked on the base 370. The semiconductor chip 373 forming a first circuit layer is reversed and as a result, the solid-state circuits 372 of the chip 373, which are located on the surface side of the chip 373, are placed at a lower position (on the side of the base 370). The solid-state circuits 372 are opposed to the solid-state circuit 371 of the base 370. Moreover, the solid-state circuits 372 are electrically connected to the solid-state circuit 371 of the base 370 by way of microbumps 381 provided on the surface (the lower surface in FIG. 10) of the chip 373. These microbumps 381 are electrically insulated from each other with non-illustrated insulating materials, respectively.
The outside shape of the semiconductor chip 373 is the same as that of the base 370. Namely, the thickness (height) of the chip 373 is different from that of the base 373 while the contour of the chips 373 is the same as that of the base 370, where the chip 373 and the base 370 are superposed on each other.
Buried electrodes 374 are formed in the semiconductor chip 373. One end of each electrode 374 is extended to the solid-state circuit 372 and connected thereto, and the other end thereof is extended to the back (the upper surface in FIG. 10) of the chip 373 and exposed. Namely, each electrode 374 penetrates through the chip 373 from the bottom of the solid-state circuit 372 to the back of the chip 373. Each electrode 374 is electrically insulated from the chip 373 with an insulating film 374a that surrounds the whole side face of the electrode 374.
On the back of the semiconductor chip 373, a semiconductor chip 376 having a solid-state circuit 375 formed in the surface region thereof is stacked. The semiconductor chip 376 forming a second circuit layer is reversed and as a result, the solid-state circuits 375 of the chip 376, which are located on the surface side of the chip 376, are placed at a lower position (on the side of the base 370). The solid-state circuits 375 are opposed to the back of the semiconductor chip 373 forming the first circuit layer. Moreover, the solid-state circuits 375 are electrically connected to the solid-state circuits 372 of the chip 373 by way of microbumps 382 provided on the surface (the lower surface in FIG. 10) of the chip 376 and the buried electrodes 374 provided in the chip 373. These microbumps 382 are electrically insulated from each other with non-illustrated insulating materials, respectively.
The outside shape of the semiconductor chip 376 is the same as those of the base 370 and the semiconductor chip 373. Namely, the thickness (height) of the chip 376 is different from those of the base 373 and the chip 373 while the contour of the chip 373 is the same as that of the base 370, where the chips 373 and 376 and the base 370 are superposed on each other. The thickness (height) of the chip 376 may be the same as that of the chip 373.
Buried electrodes 377 are formed in the semiconductor chip 376. One end of each electrode 377 is extended to the solid-state circuit 375 and connected thereto, and the other end thereof is extended to the back (the upper surface in FIG. 10) of the chip 376 and exposed. Namely, each electrode 377 penetrates through the chip 376 from the bottom of the solid-state circuit 375 to the back of the chip 376. Each electrode 377 is electrically insulated from the chip 376 with an insulating film 377a that surrounds the whole side face of the electrode 377.
A non-illustrated external electrode (e.g., a microbump or solder ball) is connected to the exposed end of each buried electrode 376 from the back of the semiconductor chip 376. The conventional three-dimensional semiconductor integrated circuit device 300 is electrically connected to an external circuit by way of these external electrodes.
Each of the solid-state circuits 371, 372, and 375 is, for example, an integrated circuit constituted by the combination of the circuit elements, such as transistors, solid-state devices, and so on formed in the active regions of the base 370 or the semiconductor chip 373 or 376, realizing a predetermined circuit function.
As the stacking type of the respective circuit layers in the aforementioned conventional three-dimensional semiconductor integrated circuit device 300, the “wafer stacking method” where wafers are successively stacked on a base and thereafter, the stacked wafers are divided into pieces, and the “chip stacking method” where semiconductor chips judged good are stacked, have ever been known.
With the “wafer stacking method”, a first wafer in which many solid-state circuits (integrated circuits) are embedded is coupled with a base in such a way that the functional elements of the first wafer are opposed to the base. Thereafter, holes are formed in the first wafer from the back side thereof by, for example, etching, and then, these holes are filled with a conductive material, thereby forming buried electrodes that extend from the solid-state circuits to the back of the first wafer. These buried electrodes serve as the electric paths for electrical connection to the aforementioned solid-state circuits. Subsequently, the same processes as those performed for the first wafer are carried out for a second wafer in which many solid-state circuits are embedded. Thereafter, the same processes are repeated, thereby forming a wafer stack that includes the base and the wafers stacked thereon. With this wafer stack, the solid-state circuits existing in the adjoining wafers are electrically interconnected to each other by way of the buried electrodes formed in the wafers. Finally, the wafer stack is diced by, for example, the blade dicing method, according to the necessity, resulting in a wafer-level three-dimensional semiconductor integrated circuit device or chip-shaped three-dimensional semiconductor integrated circuit devices. Any material may be used for the base if it can support wafers to be stacked. In addition, a semiconductor wafer may be used for the base.
Since the formation of the holes and the buried electrodes can be conducted in the wafer level in the “wafer stacking method”, the fabrication processes are simplified compared with those in the “chip stacking method”. Therefore, the “wafer stacking method” is advantageous at that point.
With the “chip stacking method”, usually, holes are formed in a single wafer in which many solid-state circuits are embedded from the back side of the wafer and then, the holes are filled with a conductive material, thereby forming buried electrodes that extend from the solid-state circuits to the back of the wafer. Next, the wafer is diced to pieces, resulting in first semiconductor chips. Thereafter, these first semiconductor chips are subjected to an operation test to sort out good ones. Subsequently, the first semiconductor chips that have been judged good are arranged on the base to have a predetermined layout. Next, second semiconductor chips that have been obtained in the same way as the first semiconductor chips and judged good are stacked on the corresponding first semiconductor chips. The solid-state circuits existing in the first and second semiconductor chips thus stacked are electrically interconnected to each other with the buried electrodes formed therein. After that, these processes are repeated, thereby forming chip stacks each having the semiconductor chips stacked on the base. Finally, the chip stacks are diced by, for example, the blade dicing method, according to the necessity, resulting in a wafer-level three-dimensional semiconductor integrated circuit device or chip-shaped three-dimensional semiconductor integrated circuit devices.
Alternately, the chip stack may be formed by directly stacking a corresponding one of the second semiconductor chips on each of the first semiconductor chips without using the base. In this case, the dicing process is unnecessary.
With the “chip stacking method”, the semiconductor chips comprising the electrical paths that have been formed on their surfaces and backs beforehand and that have been judged good are stacked and therefore, the “chip stacking method” is advantageous in fabrication yield compared with the “wafer stacking method”.    Patent Literature 1: Japanese Non-Examined Patent Publication No. 2001-250913